Job Description for openings at Neuron IP Spain

In-office, some Hybrid work possible.  

Neuron IP is actively seeking a Digital ASIC Engineer in Design, Verification, and/or Firmware to be an integral part of our die-to-die interface protocol team, focusing on cutting-edge UCIe chiplets for use in AI/ML, HPC, and automotive. This role is for you if you are passionate about advancing digital communication protocols, disaggregating monolithic SoCs, and building open-source ecosystems. 

The Role: 

In this vital role, you will contribute to the creation and realization of state-of-the-art die-to-die interface designs. Working closely with the front-end design and integration team, you will collaborate with architects, IP designers, firmware engineers, Physical Design, and product engineers to achieve first-rate silicon success. Explore application verticals such as hardware security modules, artificial intelligence hardware architectures, memory interfaces, protocols to enable cloud compute Systems-In-Packages (SiPs), and chiplet requirements for automotive platforms.  

The Person: 

We are looking for someone with at least 4 years of focused, practical experience, with a steadfast commitment to delivering high-quality results on schedule. You will have a zeal for learning and excellence in a technical capacity, thriving in both team-oriented and individual settings. Your communication skills will shine in meetings, presentations, and written documentation. You are an autonomous learner, eager to pick up new skills needed for your role and flexible enough to work with colleagues in different time zones. We value creative thinkers and problem-solvers who pay close attention to detail. You must be able to work in the country you’ve applied in, within an in-office model.  

The Future: 

Neuron IP is a company committed to training and growing your career on the job.  You will work with experts in the various fields of analog & digital circuits, and will be given the tools, training and exposure to quickly grow you into one such expert in the field with broad experience in ASIC RTL, and a deep expertise in high-speed wireline communications architectures. 

Key Responsibilities: 

• Join & lead the integration, implementation, and/or verification of Neuron IP's die-to-die interface PHYs, such as for UCIe. 
• Oversee IP integration, synthesis, timing, lint, and CDC closure to ensure top-tier design quality with tools from a diverse list of EDA vendors. 
• Implement design specifications related to testing, debugging, and clock configurations. 
• Identify and dissect complex technical issues, evaluate multiple solutions, and steer the team towards successful execution. 
• Drive the development of efficient workflows, including automation and scripting for design processes, firmware toolchains, verification test plans, and EDA methodologies. 
• Work in unison with teams of Firmware Engineers, Verification Engineers, RTL & IP designers, Physical Design, and SoC leaders, ensuring cross-team synergy. 
• Create & execute verification plans in conjunction with Digital, Firmware, Analog, and Systems teams.  
• Engage in detailed discussions regarding technical aspects and project schedules with engineers and managers across different sites. 

Preferred Experience: 

• Proficient understanding of Digital Design & Verification in RTL, particularly with Verilog HDL and SystemVerilog. 
• Knowledgeable about Synthesis, timing constraints, Linting, CDC tools, and conducting equivalence checks.  
• Strong skills in Linux, TCL, Python scripting, Makefiles, and other analysis & automation utilities. 
• Background in ASIC implementation and familiarity with tools from Synopsys, Cadence, and Mentor. Able to create test plans and build block level testbenches with UVM/cocotb.  
• In-depth knowledge of clocking, reset sequences, power-up sequences, and physical design optimization. Exposure to and understanding of PCIe, CXL, UCIe, and Ethernet (PHY, PCS, Protocol). 
• Knowledge of embedded C firmware, microcontrollers, and memory mapped registers. Additionally, RISC-V ISA experience is an asset.  

Academic Credentials: 

• Bachelor's or Master’s degree in Electrical/Computer Engineering, Engineering Science, Computer Science, or a related field. 
• Minimum English level (CEFR) of C1 preferred.